1. Field of the Invention
This invention relates generally to data processing systems and more particularly to apparatus including a switch which stabilizes the logic for enabling the setting of the clock timing.
2. Description of the Prior Art
As performance of data processing systems is improved by use of faster circuit components in the logic circuits, the clock cycle periods used in the CPU become shorter and accumulative tolerance that must be allowed due to component variations in the clock system circuit becomes a larger percentage of the total clock cycle period. For example, the variation may be plus or minus 5 nanoseconds in a 100 nanosecond clock cycle period for a data processing system designed for a minimum 95 nanosecond clock cycle period; this results in a plus or minus 5% variation in the clock cycle period. The same plus or minus 5 nanosecond variation in a 50 nanosecond clock cycle period results in a plus or minus 10% variation in the clock cycle period in a system designed for a minimum 45 nanosecond clock cycle period. If the clock can be adjusted during manufacturing to have a 45 nanosecond clock cycle period with a tolerance of -0 nanoseconds and +2 nanoseconds, the throughput of the worst case data processing system with an adjustable clock cycle period, one having a clock cycle period of 47 nanoseconds (45+2), can be up to 17.7% ((55-47)/45*100) better than a data processing system having a non-adjustable clock with the worst case clock cycle period of 55 nanoseconds (50+5).
Therefore, although it is desirable as mentioned hereinbefore not to have to individually adjust the clock cycle period of the system clock during manufacture, adjustment is necessary in order to maximize the throughput of the data processing system. An example of the clock system providing for the adjustment of the clock frequency is given in U.S. Pat. No. 3,775,696 entitled "Synchronous Digital System Having a Multi-Speed Logic Clock Oscillator" issued to Emory Carl Grath and incorporated herein by reference. In the clock system of U.S. Pat. No. 3,775,696, an adjustable delay line is connected in series with a fixed delay line with the output of the delay lines being fed as input to a NAND gate and the output of a NAND gate being fed as input to the delay lines as well as being used for the clock signal. In this device, the adjustable delay line is comprised of a plurality of selected lengths of copper transmission line which are etched onto any epoxy-glass circuit board onto which the remaining components are mounted, with each transmission line connecting a pair of plated terminals which extend through the printed circuit board. The propagation delay of copper etch on epoxy-glass circuit boards is approximately one nanosecond per six inches, such that each foot of transmission line introduces a two nanosecond time delay. The transmission line lengths are adaptable to be selectively interconnected by connecting the appropriate terminals, thereby introducing accumulative time delays. The lengths of the transmission line segment are binary weighted to allow introduction of a desired time delay with a minimum number of interconnections. The plurality of plated holes at the ends of the lengths of copper transmission line which comprise the adjustable delay line may be interconnected by short wire jumpers while only introducing negligible time delays.
Although the clock system of U.S. Pat. No. 3,775,696 is adjustable, it has several disadvantages. To provide for an adjustment of plus or minus 12 nanoseconds, a span of 24 nanoseconds, a minimum of 12 feet of copper etch transmission line is required and providing this may present significant problems in laying out the circuit board as more and more complex, circuits requiring more interconnects are used. In addition, the adjustment of the clock during manufacture by the placing of jumpers can be time consuming and therefore costly. Further the clock system can not be easily adjusted in the field during system maintenance to compensate for changes in clock speed due to components aging or replacement. Also the clock system can not be easily adjusted to operate the data processing system at marginal speeds to detect speed dependent problems before they impair the data processing system performance at normal operating speed.
U.S. application Ser. No. 224,727 entitled "Adjustable Clock System Having a Dynamically Selectable Clock Period" describes the use of a switch bank coupled to a multitapped delay line enabling the selective adjustment of the clock pulse width. To adjust the clock, a scope or counter is used while the clock is running. In the normal operation, the clock does not run continuously. This requires replacing the normal firmware with special firmware which is either time consuming and not easily done in the field.
It should be understood that the references cited herein are those of which the applicants are aware and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.